Login Sign Up   Invite   Feedback  
Mismatch between two array of identical MOS
Calculates 3 sigma mismatch between two arrays of identical MOS devices (same size, orientation and environment) and expresses mismatch in three different forms: referred to the gates (e.g. in a differential pair in delta Vgs ), referred to the drain (percentage of output current difference), and as DNL in a current DAC when changing DAC code input from p to q assuming p and q devices are identical but distinct. DNL is expressed as a percentage of the current in one single transistor. Note that all the formulas assume that all layout used best practice, as referred to in literature.

Block diagram

Inputs
Inversion Coefficient IC (>0)
Weak Inversion Slope n
1-sigma VT mismatch coefficient Avt mV.um
1-sigma Beta mismatch coefficient Abeta %.um
Number of devices in array A (p)
Number of devices in array B (q)
Width of each devices W um
Length of each devices L um
 
Outputs
gm/Id of the transistor 1/V
3-sigma mismatch in a differential pair structure at the gate mV
3-sigma mismatch in a current mirror %
3-sigma differential non-linearity of unity current for a binary DAC with current output, switching from p to q units %
Rate this tool:
Comments

Add a Comment
You need to be a member to comment on this!Join Circuit Sage!