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All Tips (19)
Tip 1
Check off-state leakage current in CMOS circuits with fast models and hot temperature. The leakage increases exponentially with temperature, and you may find you have to add high-Vt switch devices in the power supply to meet leakage specs over all conditions.


Tip 2
Check stability of all feedback loops, even "small, simple" ones over the range of conditions seen by the circuit. For example the output impedance, and the pole frequency, at the output of a typical LDO regulator varies with load current. If the regulator must be on with very low load, e.g. when the supplied circuits are off, then the regulator may become unstable and either the compensation may need to be adjusted or a small leakage current added. Cadence's Spectre's stb analysis provides a simple and accurate method of simulating loop gain and phase without concern for the impedances at the point where the loop is broken. Similar methods can be implemented in other simulators.


Tip 3
Minimize the number of nodes saved during simulations to maximize the speed of the simulation. Keep an eye on the simulation output file size and strive to reduce the number of nodes saved if the files are getting larger than 100MB, as disk I/O can become more limiting than the actual calculations.


Tip 4
When designing regulators for digital circuits it's important to simulate with a representative transient current of the digital circuit, and not just with average current. Power supply droop and any stability issues in the regulator can be significantly worse with the high peak currents in CMOS logic. Note that it's the rapid transitions that occur at each clock edge that matter more than the actual clock rate.


Tip 5
Include bond-wire inductance in circuit models of any circuits with high speed signals that connect to wire-bonded pads. This includes not only RF circuits and signal pads, but power supply and ground pads for single-ended digital circuits, as well. A good rule of thumb is 1nH inductance per millimeter of length.


Tip 6
It is recommended to keep Vgs-Vt of current mirrors above 200mV for good matching and noise performance


Tip 7
Always simulate common mode rejection and supply noise rejection of any circuit using mismatch in the transistors


Tip 8
Use dummy transistors at the end for current mirrors and differential pairs at the end of the row to take out poly etching loading, mask misalignment and shallow trench isolation effects


Tip 9
Always use fingers that even (preferably factors of 2) in design of current mirror as a base cell with same W and L. This will take out dW and dL effects as well as shadowing


Tip 10
Triple well can provide good isolation only up to 4GHz frequency. Make sure to model the extra well capacitance to substrate as this is not modeled in most CMOS processes


Tip 11
It is often unnecessary and undesirable to use the 3:1 ratio for PMOS:NMOS widths for standard logic gates. Modern processes are fast enough, and noise margin large enough that minimum width and length can be used for most internal logic transistors. Using minimum sized logic transistors provides benefits of reduced area (and thus routing capacitance), reduce rush through current, reduced power, and reduced noisy supply currents.


Tip 12
Linear regulators often have only a PMOS transistor at the output to drive the load. Care must taken to limit overshoot when a large load current turns off. It takes time to turn off the large PMOS transistor, which dumps current into the load capacitor after the load current turns off. Without a load current to remove the charge, the voltage can remain high for very long periods of time.


Tip 13
Opamp based bandgaps usually have both positive and negative feedback loops. Care must be taken to make sure the negative feedback loop has higher gain than the positive feedback loop. Stability analysis is performed by breaking the loop at a point that is common to both positive and negative feedback loops.


Tip 14
Despite being more complicated and having more transistors, cascoded current sources are usually much smaller than simple current mirrors for the same output resistance. Cascoded current sources typically use smaller lengths and widths compared to simple current mirrors, provided that headroom is available for the extra cascode assuming area is not limited by 1/f or matching considerations.


Tip 15
When simulating off-state current of any circuit, always run a transient simulation. Use the following transient sequence to enable/disable your circuit: {enable, disable, enable}. This will help determine if there are any floating, high-impedance nodes that can cause the off-state current to decay slowly.


Tip 16
Junction temperature can be much higher than air temperature around you application. To find the temperature difference between the air and the junction, use the following equation: Temppjunction = TempAir + Rthpackage * Pchip + PPCB * RthPCB. Rthpackage is the thermal resistance of the package, which is usually in the 25-35degC/Watt range; Pdie is the total power consumed by the chip; PPCB is the total power consumed by all of the chips on the PCB; RthPCB is the thermal resistance of the PCB is the the 20-30degC/Watt: http://www.micrel.com/_PDF/App-Hints/ah-25.pdf.


Tip 17
For short channel processes use low-leakage devices for powering down internal nodes to prevent leakage current from power down device from altering currents.


Tip 18
Route current sources not voltages, so that IR drops in the supply and ground do not affect the signals.


Tip 19
Minimize the number of current legs for lowest noise for a given current.
Example #1: single ended circuits use half the current legs and add half the number of noise elements.
Example #2: If headroom permits, telescopic opamps have half the number of current legs as folded cascode opamps and thus lower power for a given input noise requirement.