Time: June 8, 2009 from 8:00 am
Location: Cambridge, MA
Website or Map: http://web.mit.edu/professional/short-programs/courses/high_speed_io_design.html?gclid=CK3DoM_3qpoCF
Seminar Type: 3-day short program
Organized By: MIT Professional Education
Latest Activity: May 7, 2009, 3:49 pm
This course covers the circuit and system design of equalized high-speed I/Os. Today's high-speed interfaces are limited by the bandwidth of the communication channel, tight power constraints, and noise sources that differ from those in standard communication systems. The wire bandwidth limitations make straight circuit solutions inefficient and the power and area constraints make standard digital communication approaches infeasible. Efficient solutions require bridging the fields of digital communications, optimization, statistical, and dynamic system modeling with system architecture, mixed-signal, and digital circuit design. This course will lay the groundwork for this type of system-driven I/O design by covering each of the required layers in link system hierarchy.
Add a Comment
You need to be a member to comment on this! Join Circuit Sage !