Cadence Design Systems Inc, Cadence Design Foundry, Columbia MD as an Analog IC Design Engineer. 2008 – 2009
• Clock Trees – custom design and verification of Clock Trees as a part of SERDES macro:
o Designed Quadrature Phase Clock trees
Masters’ Graduate in Electrical Engineering, State University of New York, Stony Brook. 2006 – 2007
• Continuous time Delta Sigma Modulator:
o Designed and physically implemented (layout) second order continuous time Delta Sigma Modulator sampled at 26MHz with a signal bandwidth of 270 KHz.
• Fully differential CM feedback two stage OP-Amp:
o Designed and physically implemented (layout) an OP-Amp with 100dB gain, 1 mW power consumption and 50 ns settling time.
• SPU – Design and simulation of Synergistic Processor Unit an element of Sony’s Cell Microprocessor:
o SPU, a pipelined Graphic Processor Unit (GPU) had a dual instruction, SIMD (single instruction multiple data) architecture.
o Potential problems like Data Hazards were eliminated using advance techniques like
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