PLL Design
A Phase-Locked Loop (PLL) is a closed-loop circuit that compares its output phase with the phase of an incoming reference signal and adjusts itself until both are aligned, i.e., the PLL output's phase is "locked" to that of the input reference. Once the loop is locked (the phase ...
Circuit Sage Tools WEB TOOLS PLL 2nd order loop filter design program:Enter LG, CP current, Fr, Fout, and BW, program outputs filter values and divider ratio PLL Loop Filter Design Type 2 with Extra Pole:This tool calculates PLL loop components of Type 2 PLL with extra pole MATHCAD/MATLAB Second order PLL Mathcad design routine:Analysis of a second-order PLL with passive filter and current-mode phase detector Second order PLL Mathcad design routine (pdf):.pdf file of second-order PLL routine Third order PLL Mathcad design routine:Analysis of the charge-pump-based third order PLL Third order PLL Mathcad design routine (pdf):.pdf file of third order PLL routine Third order boosted PLL Mathcad routine:Analysis of a third order PLL boosted with a higher CP current for faster settling time Third order boosted PLL Mathcad routine (pdf):.pdf of third order boosted PLL routine Third order, switched resistor, boosted PLL:Analysis of a third order PLL in which the filter resistor is switched during the "boost" mode of operation Third order, switched resistor, boosted PLL (pdf):.pdf of switched-resistor, boosted, third order PLL Crystal oscillator routine:Mathcad routine analyzes a crystal's equivalent circuit Online Tools MATHCAD/MATLAB Simulink Charge Pump PLL design tool:Enter VCO parameters and a loop filter's poles/zeros to obtain the outputs of the filter, VCO, and PFD Lance Lascari:Estimates phase noise from the various sources in the PLL, incl. op-amps. Also .pdf copy of Applied Wireless magazine article National:Mathcad files to help you design a PLL Mathcad Explorer 8:Free viewer allows to view and edit (but not save) Mathcad files, works up to Mathcad 8.0 Mathcad Direct Digital Synthesis tools:11 Mathcad routines plus some videos of the software in action! DDS simulator for MATLAB:Martin Pechanec's tool uses a GUI SOFTWARE PLL Design Assistant:Part of CPPSim, takes as input a desired transfer function and calculates the open-loop parameters required to achieve the design CPPSim 3:CppSim is a free behavioral simulation package that leverages the C language to allow very fast simulation of systems. Users enter designs in a graphical schematic editor, Sue2, run the simulations using a provided GUI tool, and then view the results within CppSimView (a custom waveform viewer for CppSim). Users can also run simulations and plot signals directly within Matlab. PLL:DOS-looking tool to design a PLL Radiolab SimPLL:$495, free demo available Elekta 2.0:$99 from Scitechpub, PLL tool is just one of many tools Blake PLL Analysis Program:Originally published in a trade magazine Nathan Iyer's PLLSim (FREE!):Free tool to design your PLL WEB TOOLS Interactive Digital PLL Design:Design of 2nd order PLL using some input parameters National EasyPLL simulator:Helps design a PLL using National's Ics Third order PLL filter calculator:From Green Bay Professional Packet Radio, calculates loop filter components from PLL system parameters Hittite PLL phase noise calculator:Interactive tool allows you to see the PLL phase noise as well as the contributions from each component Online Articles Delta-sigma Frac-N for WLAN paper:Compatible with 2.4 and 5 GHz WLAN, achieves less than 1 degree of integrated phase noise A fast-locking scheme for PLL frequency synthesizers:Discusses boosting the PLL lock time by using an auxiliary charge pump Dean Banerjees's PLL Performance, Simulation, and Design Handbook:**Very good** reference for PLL design. Printed copy available through Amazon Integrating the PLL system on a chip:Discusses issues associated with integrating various PLL blocks in a single chip PLL Building Blocks:Overview of the PLL components and equations Loop Filter Optimization:How to optimize the loop filter design given the system parameters Passive loop filter design techniques for a third order charge pump PLL:Detailed analysis of PLL system equations Freescale's PLL Design Fundamentals:Basic equations for stability, bandwidth, and an example TI's Fractional/Integer-N Basics:In-depth article covers most topics of interest Synergy's Synthesizer Design for Microwave Applications:Comprehensive article, very good read Design and measurement of a 400-MHz synthesizer:Using Eagleware (now Agilent) tools, design a 400 MHz PLL and contrasts simulation results with the lab's. DDS presentation:Performance of a DDS in a GaAs process DDS spectrum:Towards the middle of the page, analyzes output spectrum of a DDS Principles of PLLs:From Venceslav Kroupa, comprehensive tutorial John Maneatis' articles and white papers on PLL design:IEEE JSSC conference papers on low-jitter PLLs and other topics CML divider that works at 17 GHz: paper from UC - Irvine:20% faster than standard latch in 0.18 um CMOS process CMOS PLL presentation from UC-Berkeley:Fully integrated CMOS PLL with differential, active loop filter Wideband PLL PhD thesis:Presents a wideband PLL architecture, includes fully integrated and differential loop filter. Fully integrated Fractional-N synthesizer:Frac-N synthesizer in 0.25um CMOS Wideband PLL thesis:Discusses a wideband PLL that could potentially be used in multiple communications standards Frac-N synthesizer for 900-MHz band thesis:Frac-N synthesizer implemented in 0.18 um process Designing loop filters for PLL's:Fujitsu article on how to design a 3-pole LF A wideband, low phase noise VCO paper from UC-Berkeley:75-MHz/V, low phase noise VCO implemented in 0.25-um CMOS Frac-N Synthesizer for wireless communications Phd thesis from Georgia Tech:Implemented in 0.18-um CMOS, incorporates FIR digital loop filter instead of analog filter Precise oscillator control in PLL's Phd thesis from Georgia Tech:Presents process-tolerant techniques to accurately control the PLL VCO at multi-GHz frequencies, demonstrates in 0.18-um CMOS PLL with constant bandwidth for DVB-T paper from Fudan U.:1.2-2.0 GHz synthesizer,techniques to make loop bandwidth constant across output frequency range Delta-sigma PLL's with dithred division ratios app note from Agilent:Delta-sigma PLL with dithered division ratio for reduced spurs, analysis in ADS A Technical Tutorial on Digital Signal Synthesis from ADI:Comprehensive document on DDS fundamentals and applications Frac-N using divide-by1.5 cell paper from National Taiwan University:Presents programmable cell that divides by 1 or 1.5 and uses it to implement a 128-255.5 fractional divider with 0.5 steps. Prototypes in 0.18 micron CMOS. Overview of frequency divider topologies at MIT OCW (Perrott):Various topologies pros/cons examined. Part of an OCW course. Brief overview of frequency dividers article from RF Design:Analog (millimeter-wave) and digital approaches to frequency division Various synthesizer lectures from MIT OCW course:Lectures 11 through 18, very good stuff Wideband Frac-N for DMB tuners paper from Kwangwoon University in Seoul:Covers UHF and VHF band with a single VCO by using a pseudo-exponential capacitor bank that reduces KVCO variation and frequency step size per bit code. Implemented in 0.18-um CMOS PLL design consederations: presentation from UT - Austin:Qualitative analysis of the issues involved in selecting topologies of the various PLL blocks Hybrid Frac-N/Integer-N PLL paper from Harvard:Best-of-both-worlds PLL topology is Frac-N during transient to accelerate phase locking and Integer-N in steady state. Demonstrates in 0.18-um CMOS. Low-voltage charge pump generates Vdd*3.75-level output pulses paper from U. of Washington:Charge pump topology can generate output voltages of 3.75*Vdd and also can operate from 0.4-1.2 Volts supplies. Demonstrated in 0.13-micron CMOS. Georgia Tech lecture on charge pumps and loop filters:Various CP and filter topologies Woogeun Rhee's thesis on Frac-N synthesizers:Multi-bit sigma delta technique to reduce Frac-N PLL spurs. Demonstrates with a 900-MHz PLL with 1-Hz resolution and -95 dBc ref. spur in 0.5-um CMOS. OSCILLATORS Articles about oscillators:Collection of articles about oscillators Oscillators' articles and links:Articles and links about oscillators from Spread Spectrum Scene 5-GHz VCO thesis:5-GHz VCO in 0.25-um BiCMOS ARRL's Low phase noise oscillator design:Topologies, techniques, and design with ARRL's Radio Designer Caltech VCO paper:Fundamentals of oscillator phase noise analyzed and a design technique presented. 2.4-GHz, 0.35-um process Oscillator phase noise paper:Sources of phase noise and how to model it Analysis and Design of Silicon Bipolar Distributed Oscillators:Distributed 12-GHZ and 17-GHz oscillators demonstrated in 0.35um BiCMOS. Modeling of silicon transmission lines explained Jitter and Phase Noise in Ring Oscillators:Phase Noise estimations w=for CMOS ring oscillators, verified with test chip Phase Noise in LC Oscillators paper from UC-Berkeley:Analysis of phase noise in LC oscillators The Effect of Substrate Noise on VCO Performance paper from MIT:Effects of substrate noise on VCO performance as a function of isolation, bias, and center frequency are explored Slides for Effects of Substrate Noise on VCO Performance paper from MIT:Presentation on effects of substrate noise on VCO performance Oscillator phase noise analysis using SpectreRF:Learn how SpectreRF goes about calculating phase noise Wideband VCO paper from Kwangwoon University in Seoul:Pseudo-exponential capacitor bank allows for reduced KVCO variation and frequency step per bit code in octave-bandwidth VCO. Implemented in 0.18 micron CMOS Jitter in ring oscillators PhD thesis from Boston U:Analysis of sources of jitter, correlation of time- and frequency-domain measures of jitter, and a constrained-based measure to design ring oscillators to meet a desired jitter performance. Demonstrates methodology with a 155 MHz clock recovery PLL designed for an ADI part in one of their (bipolar) processes. VCO app note and workshop from Cadence:Step by step instructions on how to setup various VCO test benches in Cadence. Need to join edaboards (free). PHASE NOISE / SPURS Techniques for measuring phase noise:Measuring the phase noise of a crystal using a loop Substrate noise papers:Substrate noise coupling effects, techniques, and simulation tools Crosstalk articles:Doug Brooks' articles about crosstalk and other topics Electromagnetic Compatibility Society newsletters:IEEE newsletters have very good papers on a variety of topics On-chip inductance at 0.13-um node:EETimes article about on-chip inductance problems on 0.13-um digital ASICs, more articles at the end Phase noise sources, characterization, and performance effects:Very nice tutorials from Applied Radio Labs Phase noise prediction articles:Lance Lascari's two-part article on phase noise prediction of PLLs (2nd paragraph) Lots of information about ground loops:Ground loops and their effects on various audio/video/network systems Phase noise in oscilators:Paper discusses the fundamentals of phase noise Phase Noise in LC Oscillators:From Kouznetsov and Meyer at Berkeley, an engineering approach to quantify oscillator phase noise Bob Pease article on ground noise:Techniques to get squeaky-clean waveforms on your trusty o-scope Maxim's Managing noise in cell phones:Noise-coupling mechanisms inside a cell phone On-chip RF Isolation Techniques by Tallis Blalack:Comparison of various on-chip noise isolation techniques Cadence presentation on on-chip isolation:Very nice, sources of coupling inside an IC and the effectiveness of various techniques to battle it Simplify PLL Design from Cadence:Techniques to shorten simulation time without sacrificing accuracy Phase Noise in Oscillators presentation:Phase noise mechanisms in oscillators Jitter and phase noise in ring oscillators paper from CalTech:Effects of power consumption, output frequency, number of stages, and other parameters on jitter and phase noise is examined. Jitter in Oscillators due to power supply noise paper from U. of Toronto:Time-domain analysis of jitter due to power supply noise. Simulating jitter using SPICE paper from Iowa State:Technique to simulate jitter in a ring oscillator using SPICE. Books Dean Banerjees's PLL Performance, Simulation, and Design Handbook:freely available for download, great resource Phase-Locked Loops: Design, Simulation, and Applications by Roland Best:Focuses on practice more than theory Frequency Synthesizers: Theory and Design by Vadim Manassewitsch:from description:...Updated to include the latest achievements in the performance of crystal-controlled oscillators, the design theory of fast-switching-time synthesizers, and an example of their practical applications, the book continues to be a complete guide for everyone who works with synthesizers..." Phase-Locked Loops for Wireless Communications by Donald Stephens:from description: "...presents a complete tutorial of phase-locked loops from analog implementations to digital and optical designs...." Design of Analog CMOS Integrated Circuits by Behzad Razavi:Very good chapter on PLLs Phase-Locked Loops Engineering Handbook for Integrated Circuits by Stanley Goldman:from description:"...To speed development and ensure effective testing, engineers can turn to this collection of practical solutions, SPICE listings, simulation techniques, and testing set-ups..." Phase-Lock Basics by William Egan:from description:"...both easy to understand and easy to customize. The text can be used as a theoretical introduction for graduate students or, when used with MATLAB simulation software, the book becomes a virtual laboratory for working professionals who want to improve their understanding of the design process and apply it to the demands of specific situations..." PLL Performance, Simulation and Design, Fourth Edition by Dean Banerjee (Amazon):If you want a printed, bound copy of this phenomenal reference. You can also download it from National's website, see earlier link |