Hey people! Here goes another question. I am designing a PLL that will use an LC differential oscillator. It's output has a 2,4V DC component and a 0,6V RF signal. How can I get this signal into a digital prescaler? The technology I am using is AMS 0.35um. It has a 3.3V bias voltage for the digital circuits(vdd= 3.3V).
I have seen designs that use a voltage amplifier to to that but I am looking for a low power solution...Suggestions?
The first stage might not have much gain, so a few stages may be needed in series. The value of the resistor trades off the self biasing robustness against the gain in the first stage. Only the first stage needs to be biased, but the following stages should have identical W/L ratios to have the same switch point. Be sure to simulate over PVT and with parasitics. Another option: If you can handle a divide-by-2 (and still meet the frequency spacing requirements), then you could implement a CML divide-by-2 and a CML-to-CMOS stage at 450MHz.