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Created by Jesal Mehta
The motivation behind eliminating off-chip components has led to recent proliferation of zero-IF receiver architectures. The block diagram for direct down conversion receiver is shown above. In this topology, the entire RF spectrum is down-converted to DC. A high roll-off low-pass filter (LPF) is used to perform the channel selection.

This topology eliminates the image problem and thus avoids the use of external high-Q image reject filters. A quadrature down-conversion generates I and Q signals for further signal processing.


Eliminating off-chip components makes this architecture attractive for integration.

Since the power level of the mirror signal is equal to or less than the desired signal, the architecture requires lower image rejection and the image reject filtering can be done on-chip.

The process of reciprocal mixing is reduced since only one LO is used to down-convert the signal.

Overall, this architecture is excellent at saving cost, die area and power consumption.


Problems caused by a static and time-varying DC offset, LO leakage and flicker noise can hamper the detection of a signal. The static DC offset problem can be corrected by using proper digital signal processor (DSP) or auto-zeroing function.

A highly linear mixer is used to avoid distortion because no filtering is provided before down-conversion.

This architecture is also more prone to the second-order intermodulation distortion product (IM2).

Similar to superheterodyne architecture, this architecture requires variable high frequency LO to perform the channel selection.

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