It is well-known that the CML or SCL DFFs can achieve high-speed divide-by-2 function. The figure attached shows a simple CML DFF. Different kind of bias for the CML is popular. 1. No current tail is utilized; 2. M3,4 and M5,6 are biased by different currrent tail I1 and I2, respectively; 3. The sampling transistor M3,4 and M5,6 share the same current tail.
Two simple DFF cell can achieve divide-by-2 function. Then, which biasing technique is better and what's the main pros and cons of corresponding method?
I am working on solving this problem now, any comment relating to this topic is welcome.
Add a Comment
You need to be a member to comment on this! Join Circuit Sage!