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Created by Poojan Wagh

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Letís say that youíve designed the circuit with a supply voltage (VDD) of 2.4 V. Itís performing very well. You meet exactly the specified linearity and noise requirements, and are within the desired current limits. The power dissipated across the PMOS and NMOS devices which dictate SNR are:

PMOS: IDP◊VDSATP = 10 mA◊0.6 V
NMOS: IDN◊VDSATN = 10 mA◊1.2 V
You have 0.6 V of headroom at the output for signal swing.

The differential input impedance is 2/gm of the NMOS transistors:

Rin = 2/gmn = VDSATN / IDN = 1.2 V / 10 mA = 120 Ω
where we have the used the relation gm = 2◊ID/VDSAT which excludes short-channel effects. Including short-channel effects changes the relationship, but won't change the conclusion of this topic.

You need a balun anyway, so you have a transformer that steps up from 50 Ω to 120 Ω

Great. The product ships and it sells well.

Your boss/customer comes by and asks you for a next generation part. They want to simplify the power regulation scheme on their products, so they absolutely have to have a 1.2 V supply. Thereís no negotiation on this supply voltage.

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