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It is well-known that the CML or SCL DFFs can achieve high-speed divide-by-2 function. The figure attached shows a simple CML DFF. Different kind of bias for the CML is popular. 1. No current tail is utilized; 2. M3,4 and M5,6 are biased by different currrent tail I1 and I2, respectively; 3. The sampling transistor M3,4 and M5,6 share the same current tail.

Two simple DFF cell can achi...

Added by Zhao,Feng (Jophy Zhao) on 2009-06-25 21:02:52

TSPC prescaler with SCL prescaler

It seems that engineers prefer the latter to the first when designing dividers after VCO. Why this happens? TSPC can operate at high frequency with low power consumption, however, not very popular. Does anybody clear about different prescaler architecture can give some comments?

Added by Zhao,Feng (Jophy Zhao) on 2009-06-17 23:17:20
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