Triple well can provide good isolation only up to 4GHz frequency. Make sure to model the extra well capacitance to substrate as this is not modeled in most CMOS processes
The workshop will offer an overview of the research activities in IC design at Lund University.
Additionally invited presentations will be given by the SoS International advisory board:
- Mike Fau...
The Symposium is recognized as one of the premiere international conferences on VLSI circuits and is held in conjunction with the Symposium on VLSI Technology. This close affiliation and two full days...
It is well-known that the CML or SCL DFFs can achieve high-speed divide-by-2 function. The figure attached shows a simple CML DFF. Different kind of bias for the CML is popular. 1. No current tail is utilized; 2. M3,4 and M5,6 are biased by different currrent tail I1 and I2, respectively; 3. The sampling transistor M3,4 and M5,6 share the same current tail.
Many are predicting death of Ultra Wideband technology in consumer and computer markets. Since 802.11 (Wi-Fi) is approaching 1GB/s speed standard and emergence of 60GHz wireless standard, UWB solutions have limited market share. How come many UWB companies have folded in recent time namely WiQuest, Tzero, Radiospire and even WiMedia Alliance. Some other UWB Companies have found other ways to sur...
It seems that engineers prefer the latter to the first when designing dividers after VCO. Why this happens? TSPC can operate at high frequency with low power consumption, however, not very popular. Does anybody clear about different prescaler architecture can give some comments?
Don't rely on the MUXout or LD out of a PLL synth compared to rising edges of data input to give you accurate lock time measurements. The LD lines tend to go high well before the final freuqency has settled to, say, within 1KHz of final freq. The only accurate method is a tranisent mode using an SSA. ...
